`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:57:12 08/12/2015
// Design Name:   MainUart
// Module Name:   D:/Libraries/Documents/Ingenieria en Comp/MIPS/trunk/Uart/UartTest.v
// Project Name:  uartc10del11
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MainUart
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module UartTest;

	// Inputs
	reg clk;
	reg reset;
	reg rx;

	// Outputs
	wire tx;
	//wire [7:0] salida;
	//wire done;
	wire run_pipe;
	wire [6:0] estado;
	wire [7:0] entrada_tx;

	// Instantiate the Unit Under Test (UUT)
	MainUart uut (
		.clk(clk), 
		.reset(reset), 
		.rx(rx), 
		.tx(tx), 
		//.salida(salida),
		//.done(done),
		.run_pipe(run_pipe),
		.estado(estado),
		.entrada_tx(entrada_tx)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 1;
		rx = 1;

		// Wait 100 ns for global reset to finish
		#100;
		reset = 0;
      rx = 0; //bit de start - tratamos de mandar una "p"
		#10400	
		rx = 0;
		#10400	
		rx = 0;
		#10400	
		rx = 0;
		#10400	
		rx = 0;
		#10400	
		rx = 1;
		#10400	
		rx = 1;
		#10400	
		rx = 1;
		#10400	
		rx = 0;
		#10400	
		rx = 1;
		

	end
	
always begin
#1 clk = ~clk;
end
      
endmodule

